DRAM is the most prevalent memory technology used in laptops, mobile phones, workstations and servers. As such, its security is paramount, yet DRAM attacks remain as viable as ever despite many attempts to resolve its security problems. The toolkit of DRAM disturb attacks has expanded with the introduction of new techniques such as Half-Double and RowPress, and it is likely that additional form of disturbance errors (and reliability and security issues) will emerge as we scale DRAM devices to smaller feature sizes. DRAM is also plagued by additional forms of attack, including side-channel, Denial-of-Service (DoS), and cold-boot attacks.
Against this backdrop, the industry is introducing new DRAM security solutions that require independent scrutiny from the academia. Academia continues to propose novel fixes for RowHammer, often without the benefit of insight into constraints faced by the industry.
Registration and workshop program
DRAMSec 2025 is co-hosted with ISCA. Information on registration for the workshops can be found here. We allow hybrid participation for DRAMSec 2025. If you are registered for the workshop, and would like to join remotely, please reach out to the Program Chairs for a link.Schedule
Updated 2025.05.22| Time JST (21st) | Time CEST (21st) | Topic |
| 09:00 - 11:00 | 02:00 - 04:00 | Session I |
| 11:00 - 11:30 | 04:00 - 04:30 | Coffee Break |
| 11:30 - 13:00 | 04:30 - 06:00 | Session II |
| 13:00 - 14:00 | 06:00 - 04:00 | Lunch Break |
Accepted papers
Softhammer: Exploiting Rowhammer Bit Flips without Crashing
Finn de Ridder, Patrick Jattke, Kaveh Razavi
Rubber Mallet: A Study of High Frequency Localized Bit Flips and Their Impact on Security
Andrew J. Adiletta, Zane Weissman, Fatemeh Khojasteh Dana, Berk Sunar, Shahin Tajik
CnC-PRAC: Coalesce, not Cache, Per Row Activation Counts for an Efficient in-DRAM Rowhammer Mitigation
Chris S. Lin, Jeonghyun Woo, Prashant J. Nair, Gururaj Saileshwar
A Simulation-based Evaluation Framework for Inter-VM RowHammer Mitigation Techniques
Hidemasa Kawasaki, Soramichi Akiyama
Sudoku: Decomposing DRAM Address Mapping into Component Functions
Minbok Wi, Seungmin Baek, Seonyong Park, Mattan Erez, Jung Ho Ahn
Counterpoint: One-Hot Counting for PRAC-Based RowHammer Mitigation
Shih-Lien Lu, Jeonghyun Woo, Prashant J. Nair
DRFM and the Art of Rowhammer Sampling
Salman Qazi, Moinuddin Qureshi
Keynote
Panel
Is PRAC a good solution to DRAM read disturbance? Are we missing anything? Can we (and should we) do much better (and hopefully not worse)?
Workshop chairs
- Onur Mutlu, ETH Zürich
- Kuljit Bains, NVIDIA
Submissions and Web Chairs
- Nisa Bostancı, ETH Zürich
- A. Giray Yağlıkçı, ETH Zürich
Program committee
- Jung Ho Ahn, Seoul National University
- Barbara Aichinger, FuturePlus Systems
- Shaahin Angizi, New Jersey Institute of Technology
- Kuljit Bains, NVIDIA
- Tanj Bennett, Avant-Gray LLC
- Jeremy Chritz, Micron
- Lucian Cojocar, Intel
- Daniel Gruss, TU Graz
- Yanan Guo, University of Rochester
- Hasan Hassan, Rivos
- Engin Ipek, Micron
- Aamer Jaleel, NVIDIA
- Jae W. Lee, Seoul National University
- Tamara Lehman, University of Colorado Boulder
- Shih-Lien Lu, Washington State University
- Michele Marazzi, ABB Research
- Prashant Nair, University of British Columbia
- Minesh Patel, Rutgers University
- Salman Qazi, Google
- Moinuddin Qureshi, Georgia Institute of Technology
- Kaveh Razavi, ETH Zürich
- Randall Rooney, Micron
- Gururaj Saileshwar, University of Toronto
- Stefan Saroiu, Microsoft
- Michael Schwarz, CISPA Helmholz
- Berk Sunar, Worcester Polytechnic Institute
- Victor van der Veen, Qualcomm
- Thomas Vogelsang, Rambus
- Christian Weis, RPTU Kaiserslautern
- Chris Wilkerson, Intel
- Steven Woo, Rambus
- Alec Wolman, Microsoft
- Fan Yao, University of Central Florida
- Yuval Yarom, Ruhr University Bochum
Sponsors
